As is well known, in a semiconductor electronic device wherein memories and macrocells are simultaneously provided, it is important to have memory matrices of a fixed size selected on the basis of the general layout of the integrated circuit or chip, and of the bulk of the macrocells in terms of silicon area. It is, therefore, important to provide sections of memory matrices which have different dimensions, so as to minimize the consumption of silicon area within the chip. FIG. 1 shows, as an example, a memory matrix 1 of conventional construction. The memory matrix 1 includes a portion 2, itself including a column multiplexer 3 for selecting a column of memory cells from a set of 2.sup.n columns.
The number of columns in the memory matrix 1 is of 2.sup.n *m, where n is the number of column address bits, and m is the number of bits which comprise the data stored in the memory matrix 1. The number of columns that can be selected by means of the multiplexer 3 determines the height X' of the portion 2. The memory matrix 1 further includes a row decoder 4 for selecting a row from a set of rows. The size of this set of rows will vary with the number of cells comprising the memory matrix 1.
In the prior art, for selecting the column of a memory address, the address least significant memory bits (LSBs) are used, whereas to select a row, the most significant bits (MSBs) are used. In this way, a mutual correspondence is established between the address and the location in the memory cell, that is, a correspondence between the electronic datum and the topological datum. Thus, the structure of the memory matrix 1 is settled by the binary logic and the manner of addressing the memory cells in the matrix.
The use of a multiplexer 3 which can select a column from a number of columns other than 2n results in either of the following situations:
1. There would be no mutual correspondence between addresses and memory locations, that is to say some addresses would have no corresponding memory cells and which is obviously unacceptable. PA1 2. The memory matrix 1 would have to be provided with a circuit for re-processing the addresses; however, such a circuit would be so inherently complicated as to be inconvenient to adopt, both because of its area requirements and of the delay it would introduce. PA1 A=address PA1 NC=number of columns PA1 ROW (ROW)=FLOOR (A/NC) PA1 COLUMN (COLUMN)=A-ROW*NC PA1 if the value of the least significant bit in the residuary row is 0, then the address relates to "even" rows and the bits of the predetermined number of bits undergo conversion by a complementation operation; and PA1 if the value of the least significant bit in the residuary row is 1, then the address relates to "odd" rows, and the bits of the predetermined number of bits undergo conversion by a translation operation.
Both situations will now be evaluated in detail. As clearly shown in the diagram of FIG. 2, it is impossible to reduce the unused space representing a waste, on the chip with the dimensions currently in use for the memory cells. The memory cells are positioned in a conventional matrix arrangement with the match between the electronic data and the topological data. As previously mentioned, binary logic places considerable constraints on the matrix size.
The standard matrix addressing logic selects a column by the least significant bits of the address. The number of columns in the matrix exhausts all of the memory locations as these bits change, thereby establishing a mutual correspondence between the electronic addresses and the physical locations in the memory matrix.
For selecting a row, the most significant bits in the memory address are similarly used. Actually, the number of rows would not always match all possible combinations of row address bits. Accordingly, some bit combinations may not be decoded, and some addresses are associated with no rows in the memory matrix. This is the case where a number of rows other than a power of two is demanded. Other memories or registers are frequently configured to correspond to such addresses, or in some cases, the addresses are left unused.
A numerical example is given here below to make the point clear. For a 48-Kbyte matrix, 16-bit memory addresses must be used, enabling a total of up to 64 Kbytes to be addressed. Thus, there will be 16 Kbytes of memory addresses that correspond to no memory locations physically within the matrix Such a memory matrix may be organized as shown in FIG. 3. The least significant bits A5-A0 select one column from a total of 64 columns, while the bits A15-A6 address one row from a total of 768 rows.
As shown best in FIG. 3, all the physical memory locations of the illustrative memory matrix are disposed in a regular sequence, that is, with one memory cell of the matrix that corresponds to each memory address from 0d to 49151d. However, for a number of columns in the matrix other than 2.sup.n, with n being an integer, the regular situation shown in FIG. 3 would no longer be obtainable. In fact, the active memory locations of the matrix would get mixed up with non-active locations, or even worse, with locations relating to other matrices in the whole memory device. For example, with 50 columns, there would be addresses, from 50d to 63d, that fail to address a physical cell in the memory, since the addresses 0d to 49151d actually address 38400 cells only.
To use a number of cells other than 2.sup.n on both sides of the memory matrix without introducing undue complication in the matrix control circuits, it could be attempted to add an input circuit for processing the incoming addresses such that one memory cell corresponds to each address. From a theoretical standpoint, the problem would be solved by the use of an input circuit adapted to execute the following algorithms:
Such a circuit should contain at least a divider and an adder/subtractor, and would be disadvantageous in requiring a very large circuit area and plural clock cycles. The last-mentioned factor adversely affects memory access time. Actually, given any number of columns, such an input processing circuit would be quite a complex in that it involves all of the address bits. Such an input processing circuit should be a second memory matrix being input addresses to be processed and outputting "processed" addresses.
To simplify the input circuit, it could be assumed to introduce an adder therein to add a constant value to each address In practice, this value would be dependent on the address itself, thereby making the input circuit even more complicated.
It could be also attempted to perform a 90-degree rotation of the memory matrix so as to have the roles of the x and y coordinates of the memory addresses exchanged, but this would not provide a satisfactory solution to the problem. As shown in FIG. 4, the number of columns still has to be a power of 2, which means that the implementable memories would be no more than 4 or 5, i.e. those corresponding to 16, 32, 64, 128 and 256 columns.
Thus, not even this solution is an acceptable one where matrices are to be a size as close as possible to that demanded by the user. The height X' of the section 2 of conventional memory matrices is, therefore, set at a value of 2.sup.n. However, the insertion of the memory matrix 1 in a chip leaves some unused areas. Hence, this results in a need to act on this fixed size of the memory matrix 1 for adapting it to the neighboring macrocells within the chip.